/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version   : O-2018.06-SP1
// Date      : Tue Nov 14 12:09:26 2023
/////////////////////////////////////////////////////////////


module BtoD_DW01_add_26 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n58, n60, n61, n62, n63, n64, n65, n66, n67;
  assign SUM[0] = A[0];

  OAI22X2 U41 ( .A0(n64), .A1(n65), .B0(n65), .B1(n66), .Y(CO) );
  INVX1 U42 ( .A(A[6]), .Y(n65) );
  XNOR2XL U43 ( .A(n67), .B(n58), .Y(SUM[3]) );
  NAND2X2 U44 ( .A(n61), .B(n62), .Y(n64) );
  NOR2XL U45 ( .A(A[4]), .B(A[5]), .Y(n66) );
  NAND2X2 U46 ( .A(n63), .B(n60), .Y(n62) );
  NAND2X2 U47 ( .A(n63), .B(SUM[1]), .Y(n61) );
  INVXL U48 ( .A(A[3]), .Y(n63) );
  INVXL U49 ( .A(n63), .Y(n67) );
  AND2XL U50 ( .A(A[1]), .B(A[2]), .Y(n58) );
  INVXL U51 ( .A(A[1]), .Y(SUM[1]) );
  INVXL U52 ( .A(A[2]), .Y(n60) );
  XNOR2X1 U53 ( .A(n60), .B(A[1]), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_25 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n58, n59, n60, n61;
  assign SUM[0] = A[0];
  assign SUM[1] = A[1];

  NAND2X2 U41 ( .A(n61), .B(n59), .Y(CO) );
  XNOR2XL U42 ( .A(n60), .B(A[2]), .Y(SUM[3]) );
  INVXL U43 ( .A(A[6]), .Y(n59) );
  AND3X2 U44 ( .A(A[3]), .B(A[4]), .C(A[2]), .Y(n58) );
  INVXL U45 ( .A(A[3]), .Y(n60) );
  NAND2X1 U46 ( .A(A[5]), .B(n58), .Y(n61) );
  INVXL U47 ( .A(A[2]), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_24 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n58, n60, n61, n62, n63, n64, n65;
  assign SUM[0] = A[0];

  OAI21X1 U41 ( .A0(n62), .A1(n63), .B0(n64), .Y(CO) );
  NOR2X1 U42 ( .A(A[1]), .B(n65), .Y(n62) );
  NAND2X2 U43 ( .A(n61), .B(n58), .Y(n65) );
  INVXL U44 ( .A(A[3]), .Y(n61) );
  INVXL U45 ( .A(A[2]), .Y(n58) );
  NAND2XL U46 ( .A(A[4]), .B(A[5]), .Y(n63) );
  XNOR2XL U47 ( .A(A[3]), .B(n60), .Y(SUM[3]) );
  INVXL U48 ( .A(A[1]), .Y(SUM[1]) );
  CLKNAND2X2 U49 ( .A(n58), .B(SUM[1]), .Y(n60) );
  INVX2 U50 ( .A(A[6]), .Y(n64) );
  XNOR2X1 U51 ( .A(A[2]), .B(A[1]), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_23 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n40, n41, n42;
  assign SUM[0] = A[0];
  assign SUM[1] = A[1];
  assign SUM[2] = A[2];

  INVX2 U22 ( .A(A[5]), .Y(n40) );
  NAND2X1 U23 ( .A(A[5]), .B(A[4]), .Y(n41) );
  INVX6 U24 ( .A(A[3]), .Y(SUM[3]) );
  INVX2 U25 ( .A(A[6]), .Y(n42) );
  OAI211X4 U26 ( .A0(SUM[3]), .A1(n40), .B0(n41), .C0(n42), .Y(CO) );
endmodule


module BtoD_DW01_add_22 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n57, n58, n59, n60, n61, n62, n64, n65;
  assign SUM[0] = A[0];

  AND2X2 U41 ( .A(n59), .B(n60), .Y(n58) );
  AND3X2 U42 ( .A(A[3]), .B(A[2]), .C(A[4]), .Y(n57) );
  INVXL U43 ( .A(A[3]), .Y(n61) );
  NAND2X2 U44 ( .A(n58), .B(n64), .Y(CO) );
  INVX2 U45 ( .A(A[6]), .Y(n60) );
  CLKNAND2X2 U46 ( .A(A[1]), .B(n57), .Y(n64) );
  INVXL U47 ( .A(A[2]), .Y(n65) );
  INVXL U48 ( .A(A[1]), .Y(SUM[1]) );
  NOR2X1 U49 ( .A(SUM[1]), .B(n65), .Y(n62) );
  INVXL U50 ( .A(A[5]), .Y(n59) );
  XNOR2X1 U51 ( .A(n61), .B(n62), .Y(SUM[3]) );
  XOR2X1 U52 ( .A(SUM[1]), .B(n65), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_21 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n46, n47, n48;
  assign SUM[0] = A[0];
  assign SUM[1] = A[1];

  OAI211X2 U29 ( .A0(SUM[2]), .A1(n46), .B0(n47), .C0(n48), .Y(CO) );
  INVX1 U30 ( .A(A[4]), .Y(n46) );
  NAND2XL U31 ( .A(A[3]), .B(A[4]), .Y(n47) );
  XNOR2XL U32 ( .A(A[3]), .B(A[2]), .Y(SUM[3]) );
  NOR2X1 U33 ( .A(A[5]), .B(A[6]), .Y(n48) );
  INVXL U34 ( .A(A[2]), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_20 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n50, n51, n53, n54, n55, n56, n57, n58, n59;
  assign SUM[0] = A[0];

  NOR2X1 U33 ( .A(n57), .B(A[6]), .Y(n54) );
  NAND2X2 U34 ( .A(n58), .B(n59), .Y(n57) );
  INVX2 U35 ( .A(A[5]), .Y(n59) );
  CLKINVX2 U36 ( .A(A[4]), .Y(n58) );
  NAND3X2 U37 ( .A(n54), .B(n55), .C(n56), .Y(CO) );
  INVXL U38 ( .A(A[3]), .Y(n50) );
  CLKNAND2X2 U39 ( .A(A[3]), .B(A[1]), .Y(n55) );
  CLKNAND2X2 U40 ( .A(A[3]), .B(A[2]), .Y(n56) );
  INVXL U41 ( .A(A[2]), .Y(n53) );
  INVXL U42 ( .A(A[1]), .Y(SUM[1]) );
  CLKNAND2X2 U43 ( .A(SUM[1]), .B(n53), .Y(n51) );
  XNOR2X1 U44 ( .A(n50), .B(n51), .Y(SUM[3]) );
  XNOR2X1 U45 ( .A(SUM[1]), .B(n53), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_15 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n55, n56, n58, n59, n60, n61, n62;
  assign SUM[0] = A[0];

  CLKNAND2X8 U39 ( .A(A[3]), .B(A[2]), .Y(n55) );
  XNOR2XL U40 ( .A(n60), .B(A[2]), .Y(SUM[2]) );
  INVXL U41 ( .A(A[1]), .Y(SUM[1]) );
  INVX2 U42 ( .A(A[1]), .Y(n60) );
  CLKINVX4 U43 ( .A(n55), .Y(n61) );
  INVXL U44 ( .A(A[2]), .Y(n59) );
  NOR2XL U45 ( .A(n59), .B(n60), .Y(n58) );
  XOR2XL U46 ( .A(A[3]), .B(n58), .Y(SUM[3]) );
  INVX4 U47 ( .A(n56), .Y(n62) );
  NAND2X8 U48 ( .A(A[4]), .B(A[1]), .Y(n56) );
  AND2X8 U49 ( .A(n61), .B(n62), .Y(CO) );
endmodule


module BtoD_DW01_add_13 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n47, n48, n50, n51, n52, n53;
  assign SUM[0] = A[0];

  INVX1 U30 ( .A(A[4]), .Y(n51) );
  CLKNAND2X2 U31 ( .A(A[2]), .B(A[3]), .Y(n53) );
  CLKNAND2X2 U32 ( .A(A[3]), .B(A[1]), .Y(n52) );
  XNOR2XL U33 ( .A(SUM[1]), .B(n50), .Y(SUM[2]) );
  XNOR2XL U34 ( .A(n47), .B(n48), .Y(SUM[3]) );
  NAND2XL U35 ( .A(SUM[1]), .B(n50), .Y(n47) );
  INVX2 U36 ( .A(A[3]), .Y(n48) );
  INVX2 U37 ( .A(A[2]), .Y(n50) );
  INVX2 U38 ( .A(A[1]), .Y(SUM[1]) );
  NAND3X2 U39 ( .A(n52), .B(n53), .C(n51), .Y(CO) );
endmodule


module BtoD_DW01_add_50 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n71, n72, n73;

  AOI21XL U54 ( .A0(A[2]), .A1(A[1]), .B0(A[3]), .Y(n71) );
  OAI22XL U55 ( .A0(n71), .A1(n73), .B0(n72), .B1(n73), .Y(CO) );
  NOR2X1 U56 ( .A(A[4]), .B(A[5]), .Y(n72) );
  INVXL U57 ( .A(A[6]), .Y(n73) );
endmodule


module BtoD_DW01_add_49 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n71, n72, n73;

  OAI21X2 U54 ( .A0(n73), .A1(n72), .B0(n71), .Y(CO) );
  INVXL U55 ( .A(A[6]), .Y(n71) );
  NAND3X2 U56 ( .A(A[2]), .B(A[3]), .C(A[4]), .Y(n72) );
  INVXL U57 ( .A(A[5]), .Y(n73) );
endmodule


module BtoD_DW01_add_48 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n71, n72, n73, n74, n75, n76;

  OAI21XL U54 ( .A0(n71), .A1(n72), .B0(n73), .Y(CO) );
  NAND2XL U55 ( .A(A[4]), .B(A[5]), .Y(n72) );
  NOR2X2 U56 ( .A(n74), .B(A[1]), .Y(n71) );
  INVXL U57 ( .A(A[2]), .Y(n75) );
  INVXL U58 ( .A(A[3]), .Y(n76) );
  NAND2X2 U59 ( .A(n75), .B(n76), .Y(n74) );
  INVXL U60 ( .A(A[6]), .Y(n73) );
endmodule


module BtoD_DW01_add_46 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n70, n71, n72, n73, n74, n75;

  OAI21XL U54 ( .A0(n74), .A1(n75), .B0(n70), .Y(CO) );
  NAND2X2 U55 ( .A(A[4]), .B(n71), .Y(n75) );
  AND2X2 U56 ( .A(n72), .B(n73), .Y(n70) );
  AND2XL U57 ( .A(A[2]), .B(A[3]), .Y(n71) );
  INVXL U58 ( .A(A[1]), .Y(n74) );
  INVXL U59 ( .A(A[6]), .Y(n72) );
  INVXL U60 ( .A(A[5]), .Y(n73) );
endmodule


module BtoD_DW01_add_45 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n55, n56, n57, n58, n59;

  OAI211X2 U38 ( .A0(n57), .A1(n59), .B0(n55), .C0(n58), .Y(CO) );
  OR2XL U39 ( .A(n59), .B(n56), .Y(n55) );
  INVXL U40 ( .A(A[3]), .Y(n56) );
  NOR2X2 U41 ( .A(A[6]), .B(A[5]), .Y(n58) );
  INVX2 U42 ( .A(A[4]), .Y(n59) );
  CLKINVX2 U43 ( .A(A[2]), .Y(n57) );
endmodule


module BtoD_DW01_add_44 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n63, n64, n65, n66, n67;

  OAI211XL U46 ( .A0(n65), .A1(n67), .B0(n63), .C0(n66), .Y(CO) );
  NOR3X1 U47 ( .A(A[6]), .B(A[4]), .C(A[5]), .Y(n66) );
  OR2XL U48 ( .A(n67), .B(n64), .Y(n63) );
  INVX1 U49 ( .A(A[3]), .Y(n67) );
  INVXL U50 ( .A(A[1]), .Y(n65) );
  INVXL U51 ( .A(A[2]), .Y(n64) );
endmodule


module BtoD_DW01_add_39 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n56, n57, n58, n59, n60, n61;
  assign SUM[0] = A[0];

  INVX6 U39 ( .A(A[2]), .Y(n57) );
  INVX6 U40 ( .A(A[1]), .Y(SUM[1]) );
  XOR2XL U41 ( .A(A[3]), .B(n56), .Y(SUM[3]) );
  XNOR2XL U42 ( .A(SUM[1]), .B(A[2]), .Y(SUM[2]) );
  NOR2XL U43 ( .A(n57), .B(SUM[1]), .Y(n56) );
  NOR2X6 U44 ( .A(n61), .B(SUM[1]), .Y(n59) );
  INVX4 U45 ( .A(A[3]), .Y(n58) );
  INVX3 U46 ( .A(A[4]), .Y(n61) );
  AND2X6 U47 ( .A(n59), .B(n60), .Y(CO) );
  NOR2X8 U48 ( .A(n58), .B(n57), .Y(n60) );
endmodule


module BtoD_DW01_add_37 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n47, n48, n49, n50, n51, n52;
  assign SUM[0] = A[0];

  NAND3X2 U30 ( .A(n51), .B(n52), .C(n50), .Y(CO) );
  INVXL U31 ( .A(A[3]), .Y(n48) );
  INVX2 U32 ( .A(A[2]), .Y(n49) );
  CLKINVX2 U33 ( .A(A[1]), .Y(SUM[1]) );
  NAND2X2 U34 ( .A(A[2]), .B(A[3]), .Y(n52) );
  NAND2X2 U35 ( .A(A[3]), .B(A[1]), .Y(n51) );
  CLKINVX2 U36 ( .A(A[4]), .Y(n50) );
  XNOR2XL U37 ( .A(n47), .B(n48), .Y(SUM[3]) );
  NAND2X2 U38 ( .A(SUM[1]), .B(n49), .Y(n47) );
  XNOR2X1 U39 ( .A(SUM[1]), .B(n49), .Y(SUM[2]) );
endmodule


module BtoD_DW01_add_51 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n3, n5;
  assign SUM[0] = A[0];
  assign SUM[1] = A[1];

  NOR2X6 U5 ( .A(A[3]), .B(A[2]), .Y(n5) );
  XNOR2XL U4 ( .A(A[3]), .B(A[2]), .Y(SUM[3]) );
  INVX18 U15 ( .A(A[4]), .Y(n3) );
  INVXL U16 ( .A(A[2]), .Y(SUM[2]) );
  NOR2X8 U17 ( .A(n5), .B(n3), .Y(CO) );
endmodule


module BtoD_DW01_add_52 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n4, n7, n9;

  NOR2X2 U22 ( .A(A[4]), .B(A[3]), .Y(n9) );
  INVX2 U23 ( .A(A[5]), .Y(n7) );
  INVXL U24 ( .A(A[6]), .Y(n4) );
  OAI21X6 U25 ( .A0(n9), .A1(n7), .B0(n4), .Y(CO) );
endmodule


module BtoD_DW01_add_53 ( A, B, CI, SUM, CO );
  input [6:0] A;
  input [6:0] B;
  output [6:0] SUM;
  input CI;
  output CO;
  wire   n3, n5;
  assign SUM[0] = A[0];
  assign SUM[1] = A[1];

  NOR2X4 U5 ( .A(A[3]), .B(A[2]), .Y(n5) );
  XNOR2XL U4 ( .A(A[3]), .B(A[2]), .Y(SUM[3]) );
  NOR2X6 U15 ( .A(n5), .B(n3), .Y(CO) );
  INVX2 U16 ( .A(A[4]), .Y(n3) );
  INVXL U17 ( .A(A[2]), .Y(SUM[2]) );
endmodule


module BtoD ( bcd_in, bcd_out );
  input [7:0] bcd_in;
  output [11:0] bcd_out;
  wire   N1, N0, rem_3_u_div_PartRem_2__2_, rem_3_u_div_PartRem_2__1_,
         rem_3_u_div_PartRem_1__3_, rem_3_u_div_PartRem_1__2_,
         rem_3_u_div_PartRem_1__1_, rem_3_u_div_SumTmp_1__3_,
         rem_3_u_div_SumTmp_1__2_, rem_3_u_div_SumTmp_1__1_,
         rem_3_u_div_SumTmp_0__3_, rem_3_u_div_SumTmp_0__2_,
         rem_3_u_div_SumTmp_0__1_, rem_3_quotient_0_,
         div_1_u_div_u_add_PartRem_1_1_n2, div_1_u_div_u_add_PartRem_1_1_n3,
         div_1_u_div_PartRem_1__7_, div_1_u_div_PartRem_1__6_,
         div_1_u_div_PartRem_1__5_, div_1_u_div_PartRem_1__4_,
         div_1_u_div_PartRem_1__3_, div_1_u_div_PartRem_1__2_,
         div_1_u_div_SumTmp_1__6_, div_1_u_div_SumTmp_1__5_,
         div_1_u_div_SumTmp_1__4_, div_1_u_div_SumTmp_1__3_,
         div_1_u_div_SumTmp_1__2_, rem_4_u_div_PartRem_1__6_,
         rem_4_u_div_PartRem_1__5_, rem_4_u_div_PartRem_1__4_,
         rem_4_u_div_PartRem_1__3_, rem_4_u_div_CryOut_1__1_,
         rem_4_u_div_CryOut_1__0_, rem_4_u_div_CryOut_2__1_,
         rem_4_u_div_CryOut_2__0_, rem_4_u_div_CryOut_3__1_,
         rem_4_u_div_CryOut_3__0_, rem_4_u_div_CryOut_5__0_,
         rem_4_u_div_CryOut_6__0_, rem_4_u_div_CryOut_7__0_,
         rem_4_u_div_SumTmp_1__1__3_, rem_4_u_div_SumTmp_1__1__2_,
         rem_4_u_div_SumTmp_1__1__1_, rem_4_u_div_SumTmp_1__1__0_,
         rem_4_u_div_SumTmp_1__0__3_, rem_4_u_div_SumTmp_1__0__2_,
         rem_4_u_div_SumTmp_1__0__1_, rem_4_u_div_SumTmp_1__0__0_,
         rem_4_u_div_SumTmp_2__1__3_, rem_4_u_div_SumTmp_2__1__2_,
         rem_4_u_div_SumTmp_2__1__1_, rem_4_u_div_SumTmp_2__1__0_,
         rem_4_u_div_SumTmp_2__0__3_, rem_4_u_div_SumTmp_2__0__2_,
         rem_4_u_div_SumTmp_2__0__1_, rem_4_u_div_SumTmp_2__0__0_,
         rem_4_u_div_SumTmp_3__1__3_, rem_4_u_div_SumTmp_3__1__2_,
         rem_4_u_div_SumTmp_3__1__1_, rem_4_u_div_SumTmp_3__1__0_,
         rem_4_u_div_SumTmp_3__0__3_, rem_4_u_div_SumTmp_3__0__2_,
         rem_4_u_div_SumTmp_3__0__1_, rem_4_u_div_SumTmp_3__0__0_,
         rem_4_u_div_SumTmp_4__0__3_, rem_4_u_div_SumTmp_4__0__2_,
         rem_4_u_div_SumTmp_4__0__1_, rem_4_u_div_SumTmp_4__0__0_,
         rem_4_u_div_SumTmp_5__0__3_, rem_4_u_div_SumTmp_5__0__2_,
         rem_4_u_div_SumTmp_5__0__1_, rem_4_u_div_SumTmp_5__0__0_,
         rem_4_u_div_SumTmp_6__0__3_, rem_4_u_div_SumTmp_6__0__2_,
         rem_4_u_div_SumTmp_6__0__1_, rem_4_u_div_SumTmp_6__0__0_,
         rem_4_u_div_SumTmp_7__0__3_, rem_4_u_div_SumTmp_7__0__2_,
         rem_4_u_div_SumTmp_7__0__1_, rem_4_u_div_SumTmp_7__0__0_,
         rem_4_quotient_2_, div_2_u_div_PartRem_1__6_,
         div_2_u_div_PartRem_1__5_, div_2_u_div_PartRem_1__4_,
         div_2_u_div_PartRem_1__3_, div_2_u_div_CryOut_1__1_,
         div_2_u_div_CryOut_1__0_, div_2_u_div_CryOut_2__1_,
         div_2_u_div_CryOut_2__0_, div_2_u_div_CryOut_3__1_,
         div_2_u_div_CryOut_3__0_, div_2_u_div_CryOut_5__0_,
         div_2_u_div_CryOut_6__0_, div_2_u_div_CryOut_7__0_,
         div_2_u_div_SumTmp_1__1__3_, div_2_u_div_SumTmp_1__1__2_,
         div_2_u_div_SumTmp_1__1__1_, div_2_u_div_SumTmp_1__1__0_,
         div_2_u_div_SumTmp_2__1__3_, div_2_u_div_SumTmp_2__1__2_,
         div_2_u_div_SumTmp_2__1__1_, div_2_u_div_SumTmp_2__1__0_,
         div_2_u_div_SumTmp_3__1__3_, div_2_u_div_SumTmp_3__1__2_,
         div_2_u_div_SumTmp_3__1__1_, div_2_u_div_SumTmp_3__1__0_, n1, n3, n4,
         n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n17, n18, n19, n20, n21,
         n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
         n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
         n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
         n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
         n78, n79, n80, n81, n82, n83, SYNOPSYS_UNCONNECTED_1,
         SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3,
         SYNOPSYS_UNCONNECTED_4, SYNOPSYS_UNCONNECTED_5,
         SYNOPSYS_UNCONNECTED_6, SYNOPSYS_UNCONNECTED_7,
         SYNOPSYS_UNCONNECTED_8, SYNOPSYS_UNCONNECTED_9,
         SYNOPSYS_UNCONNECTED_10, SYNOPSYS_UNCONNECTED_11,
         SYNOPSYS_UNCONNECTED_12, SYNOPSYS_UNCONNECTED_13,
         SYNOPSYS_UNCONNECTED_14, SYNOPSYS_UNCONNECTED_15,
         SYNOPSYS_UNCONNECTED_16, SYNOPSYS_UNCONNECTED_17,
         SYNOPSYS_UNCONNECTED_18, SYNOPSYS_UNCONNECTED_19,
         SYNOPSYS_UNCONNECTED_20, SYNOPSYS_UNCONNECTED_21,
         SYNOPSYS_UNCONNECTED_22, SYNOPSYS_UNCONNECTED_23,
         SYNOPSYS_UNCONNECTED_24, SYNOPSYS_UNCONNECTED_25,
         SYNOPSYS_UNCONNECTED_26, SYNOPSYS_UNCONNECTED_27,
         SYNOPSYS_UNCONNECTED_28, SYNOPSYS_UNCONNECTED_29,
         SYNOPSYS_UNCONNECTED_30, SYNOPSYS_UNCONNECTED_31,
         SYNOPSYS_UNCONNECTED_32, SYNOPSYS_UNCONNECTED_33,
         SYNOPSYS_UNCONNECTED_34, SYNOPSYS_UNCONNECTED_35,
         SYNOPSYS_UNCONNECTED_36, SYNOPSYS_UNCONNECTED_37,
         SYNOPSYS_UNCONNECTED_38, SYNOPSYS_UNCONNECTED_39,
         SYNOPSYS_UNCONNECTED_40, SYNOPSYS_UNCONNECTED_41,
         SYNOPSYS_UNCONNECTED_42, SYNOPSYS_UNCONNECTED_43,
         SYNOPSYS_UNCONNECTED_44, SYNOPSYS_UNCONNECTED_45,
         SYNOPSYS_UNCONNECTED_46, SYNOPSYS_UNCONNECTED_47,
         SYNOPSYS_UNCONNECTED_48, SYNOPSYS_UNCONNECTED_49,
         SYNOPSYS_UNCONNECTED_50, SYNOPSYS_UNCONNECTED_51,
         SYNOPSYS_UNCONNECTED_52, SYNOPSYS_UNCONNECTED_53,
         SYNOPSYS_UNCONNECTED_54, SYNOPSYS_UNCONNECTED_55,
         SYNOPSYS_UNCONNECTED_56, SYNOPSYS_UNCONNECTED_57,
         SYNOPSYS_UNCONNECTED_58, SYNOPSYS_UNCONNECTED_59,
         SYNOPSYS_UNCONNECTED_60, SYNOPSYS_UNCONNECTED_61,
         SYNOPSYS_UNCONNECTED_62, SYNOPSYS_UNCONNECTED_63,
         SYNOPSYS_UNCONNECTED_64, SYNOPSYS_UNCONNECTED_65,
         SYNOPSYS_UNCONNECTED_66, SYNOPSYS_UNCONNECTED_67,
         SYNOPSYS_UNCONNECTED_68, SYNOPSYS_UNCONNECTED_69,
         SYNOPSYS_UNCONNECTED_70, SYNOPSYS_UNCONNECTED_71,
         SYNOPSYS_UNCONNECTED_72, SYNOPSYS_UNCONNECTED_73,
         SYNOPSYS_UNCONNECTED_74, SYNOPSYS_UNCONNECTED_75,
         SYNOPSYS_UNCONNECTED_76, SYNOPSYS_UNCONNECTED_77,
         SYNOPSYS_UNCONNECTED_78, SYNOPSYS_UNCONNECTED_79,
         SYNOPSYS_UNCONNECTED_80, SYNOPSYS_UNCONNECTED_81,
         SYNOPSYS_UNCONNECTED_82, SYNOPSYS_UNCONNECTED_83,
         SYNOPSYS_UNCONNECTED_84, SYNOPSYS_UNCONNECTED_85,
         SYNOPSYS_UNCONNECTED_86, SYNOPSYS_UNCONNECTED_87,
         SYNOPSYS_UNCONNECTED_88;

  ADDHX1 div_1_u_div_u_add_PartRem_1_1_U2 ( .A(bcd_in[7]), .B(
        div_1_u_div_u_add_PartRem_1_1_n2), .CO(bcd_out[9]), .S(
        div_1_u_div_SumTmp_1__6_) );
  MX2X1 div_1_u_div_u_mx_PartRem_0_1_1 ( .A(bcd_in[2]), .B(bcd_in[2]), .S0(
        bcd_out[9]), .Y(div_1_u_div_PartRem_1__2_) );
  MX2X1 div_1_u_div_u_mx_PartRem_0_1_2 ( .A(bcd_in[3]), .B(
        div_1_u_div_SumTmp_1__2_), .S0(bcd_out[9]), .Y(
        div_1_u_div_PartRem_1__3_) );
  MX2X1 div_1_u_div_u_mx_PartRem_0_1_3 ( .A(bcd_in[4]), .B(
        div_1_u_div_SumTmp_1__3_), .S0(bcd_out[9]), .Y(
        div_1_u_div_PartRem_1__4_) );
  MX2X1 div_1_u_div_u_mx_PartRem_0_1_4 ( .A(bcd_in[5]), .B(
        div_1_u_div_SumTmp_1__4_), .S0(bcd_out[9]), .Y(
        div_1_u_div_PartRem_1__5_) );
  MX2X1 div_1_u_div_u_mx_PartRem_0_1_5 ( .A(bcd_in[6]), .B(
        div_1_u_div_SumTmp_1__5_), .S0(bcd_out[9]), .Y(
        div_1_u_div_PartRem_1__6_) );
  BtoD_DW01_add_26 rem_4_u_div_u_add_PartRem_0_7 ( .A({n7, 
        rem_4_u_div_PartRem_1__5_, rem_4_u_div_PartRem_1__4_, 
        rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b0, 1'b1, 1'b1, 1'b1, 
        1'b0, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_1, 
        SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3, 
        rem_4_u_div_SumTmp_7__0__3_, rem_4_u_div_SumTmp_7__0__2_, 
        rem_4_u_div_SumTmp_7__0__1_, rem_4_u_div_SumTmp_7__0__0_}), .CO(
        rem_4_u_div_CryOut_7__0_) );
  BtoD_DW01_add_25 rem_4_u_div_u_add_PartRem_0_6 ( .A({n7, 
        rem_4_u_div_PartRem_1__5_, rem_4_u_div_PartRem_1__4_, 
        rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b0, 1'b0, 1'b0, 
        1'b0, 1'b1, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_4, 
        SYNOPSYS_UNCONNECTED_5, SYNOPSYS_UNCONNECTED_6, 
        rem_4_u_div_SumTmp_6__0__3_, rem_4_u_div_SumTmp_6__0__2_, 
        rem_4_u_div_SumTmp_6__0__1_, rem_4_u_div_SumTmp_6__0__0_}), .CO(
        rem_4_u_div_CryOut_6__0_) );
  BtoD_DW01_add_24 rem_4_u_div_u_add_PartRem_0_5 ( .A({n7, 
        rem_4_u_div_PartRem_1__5_, rem_4_u_div_PartRem_1__4_, 
        rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b0, 1'b0, 1'b1, 
        1'b1, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_7, 
        SYNOPSYS_UNCONNECTED_8, SYNOPSYS_UNCONNECTED_9, 
        rem_4_u_div_SumTmp_5__0__3_, rem_4_u_div_SumTmp_5__0__2_, 
        rem_4_u_div_SumTmp_5__0__1_, rem_4_u_div_SumTmp_5__0__0_}), .CO(
        rem_4_u_div_CryOut_5__0_) );
  BtoD_DW01_add_23 rem_4_u_div_u_add_PartRem_0_4 ( .A({
        rem_4_u_div_PartRem_1__6_, rem_4_u_div_PartRem_1__5_, 
        rem_4_u_div_PartRem_1__4_, rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), 
        .B({1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_10, SYNOPSYS_UNCONNECTED_11, 
        SYNOPSYS_UNCONNECTED_12, rem_4_u_div_SumTmp_4__0__3_, 
        rem_4_u_div_SumTmp_4__0__2_, rem_4_u_div_SumTmp_4__0__1_, 
        rem_4_u_div_SumTmp_4__0__0_}), .CO(rem_4_quotient_2_) );
  BtoD_DW01_add_22 rem_4_u_div_u_add_PartRem_0_3 ( .A({n7, 
        rem_4_u_div_PartRem_1__5_, rem_4_u_div_PartRem_1__4_, 
        rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b1, 1'b0, 1'b0, 
        1'b0, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_13, 
        SYNOPSYS_UNCONNECTED_14, SYNOPSYS_UNCONNECTED_15, 
        rem_4_u_div_SumTmp_3__0__3_, rem_4_u_div_SumTmp_3__0__2_, 
        rem_4_u_div_SumTmp_3__0__1_, rem_4_u_div_SumTmp_3__0__0_}), .CO(
        rem_4_u_div_CryOut_3__0_) );
  BtoD_DW01_add_21 rem_4_u_div_u_add_PartRem_0_2 ( .A({
        rem_4_u_div_PartRem_1__6_, rem_4_u_div_PartRem_1__5_, 
        rem_4_u_div_PartRem_1__4_, rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), 
        .B({1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_16, SYNOPSYS_UNCONNECTED_17, 
        SYNOPSYS_UNCONNECTED_18, rem_4_u_div_SumTmp_2__0__3_, 
        rem_4_u_div_SumTmp_2__0__2_, rem_4_u_div_SumTmp_2__0__1_, 
        rem_4_u_div_SumTmp_2__0__0_}), .CO(rem_4_u_div_CryOut_2__0_) );
  BtoD_DW01_add_20 rem_4_u_div_u_add_PartRem_0_1 ( .A({n7, 
        rem_4_u_div_PartRem_1__5_, rem_4_u_div_PartRem_1__4_, 
        rem_4_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b1, 1'b1, 1'b0, 
        1'b1, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_19, 
        SYNOPSYS_UNCONNECTED_20, SYNOPSYS_UNCONNECTED_21, 
        rem_4_u_div_SumTmp_1__0__3_, rem_4_u_div_SumTmp_1__0__2_, 
        rem_4_u_div_SumTmp_1__0__1_, rem_4_u_div_SumTmp_1__0__0_}), .CO(
        rem_4_u_div_CryOut_1__0_) );
  BtoD_DW01_add_15 rem_4_u_div_u_add_PartRem_1_3 ( .A({1'b0, 1'b0, bcd_in[7:3]}), .B({1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_22, SYNOPSYS_UNCONNECTED_23, 
        SYNOPSYS_UNCONNECTED_24, rem_4_u_div_SumTmp_3__1__3_, 
        rem_4_u_div_SumTmp_3__1__2_, rem_4_u_div_SumTmp_3__1__1_, 
        rem_4_u_div_SumTmp_3__1__0_}), .CO(rem_4_u_div_CryOut_3__1_) );
  BtoD_DW01_add_13 rem_4_u_div_u_add_PartRem_1_1 ( .A({1'b0, 1'b0, bcd_in[7:3]}), .B({1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_25, SYNOPSYS_UNCONNECTED_26, 
        SYNOPSYS_UNCONNECTED_27, rem_4_u_div_SumTmp_1__1__3_, 
        rem_4_u_div_SumTmp_1__1__2_, rem_4_u_div_SumTmp_1__1__1_, 
        rem_4_u_div_SumTmp_1__1__0_}), .CO(rem_4_u_div_CryOut_1__1_) );
  BtoD_DW01_add_50 div_2_u_div_u_add_PartRem_0_7 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, n5, 
        div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b0, 1'b1, 1'b1, 1'b1, 
        1'b0, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_28, 
        SYNOPSYS_UNCONNECTED_29, SYNOPSYS_UNCONNECTED_30, 
        SYNOPSYS_UNCONNECTED_31, SYNOPSYS_UNCONNECTED_32, 
        SYNOPSYS_UNCONNECTED_33, SYNOPSYS_UNCONNECTED_34}), .CO(
        div_2_u_div_CryOut_7__0_) );
  BtoD_DW01_add_49 div_2_u_div_u_add_PartRem_0_6 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, n5, 
        div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b0, 1'b0, 1'b0, 
        1'b0, 1'b1, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_35, 
        SYNOPSYS_UNCONNECTED_36, SYNOPSYS_UNCONNECTED_37, 
        SYNOPSYS_UNCONNECTED_38, SYNOPSYS_UNCONNECTED_39, 
        SYNOPSYS_UNCONNECTED_40, SYNOPSYS_UNCONNECTED_41}), .CO(
        div_2_u_div_CryOut_6__0_) );
  BtoD_DW01_add_48 div_2_u_div_u_add_PartRem_0_5 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, n5, 
        div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b0, 1'b0, 1'b1, 
        1'b1, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_42, 
        SYNOPSYS_UNCONNECTED_43, SYNOPSYS_UNCONNECTED_44, 
        SYNOPSYS_UNCONNECTED_45, SYNOPSYS_UNCONNECTED_46, 
        SYNOPSYS_UNCONNECTED_47, SYNOPSYS_UNCONNECTED_48}), .CO(
        div_2_u_div_CryOut_5__0_) );
  BtoD_DW01_add_46 div_2_u_div_u_add_PartRem_0_3 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, n5, 
        div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b1, 1'b0, 1'b0, 
        1'b0, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_49, 
        SYNOPSYS_UNCONNECTED_50, SYNOPSYS_UNCONNECTED_51, 
        SYNOPSYS_UNCONNECTED_52, SYNOPSYS_UNCONNECTED_53, 
        SYNOPSYS_UNCONNECTED_54, SYNOPSYS_UNCONNECTED_55}), .CO(
        div_2_u_div_CryOut_3__0_) );
  BtoD_DW01_add_45 div_2_u_div_u_add_PartRem_0_2 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, 
        div_2_u_div_PartRem_1__4_, div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), 
        .B({1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_56, SYNOPSYS_UNCONNECTED_57, 
        SYNOPSYS_UNCONNECTED_58, SYNOPSYS_UNCONNECTED_59, 
        SYNOPSYS_UNCONNECTED_60, SYNOPSYS_UNCONNECTED_61, 
        SYNOPSYS_UNCONNECTED_62}), .CO(div_2_u_div_CryOut_2__0_) );
  BtoD_DW01_add_44 div_2_u_div_u_add_PartRem_0_1 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, n5, 
        div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), .B({1'b1, 1'b1, 1'b1, 1'b0, 
        1'b1, 1'b0, 1'b1}), .CI(1'b1), .SUM({SYNOPSYS_UNCONNECTED_63, 
        SYNOPSYS_UNCONNECTED_64, SYNOPSYS_UNCONNECTED_65, 
        SYNOPSYS_UNCONNECTED_66, SYNOPSYS_UNCONNECTED_67, 
        SYNOPSYS_UNCONNECTED_68, SYNOPSYS_UNCONNECTED_69}), .CO(
        div_2_u_div_CryOut_1__0_) );
  BtoD_DW01_add_39 div_2_u_div_u_add_PartRem_1_3 ( .A({1'b0, 1'b0, bcd_in[7:3]}), .B({1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_70, SYNOPSYS_UNCONNECTED_71, 
        SYNOPSYS_UNCONNECTED_72, div_2_u_div_SumTmp_3__1__3_, 
        div_2_u_div_SumTmp_3__1__2_, div_2_u_div_SumTmp_3__1__1_, 
        div_2_u_div_SumTmp_3__1__0_}), .CO(div_2_u_div_CryOut_3__1_) );
  BtoD_DW01_add_37 div_2_u_div_u_add_PartRem_1_1 ( .A({1'b0, 1'b0, bcd_in[7:3]}), .B({1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_73, SYNOPSYS_UNCONNECTED_74, 
        SYNOPSYS_UNCONNECTED_75, div_2_u_div_SumTmp_1__1__3_, 
        div_2_u_div_SumTmp_1__1__2_, div_2_u_div_SumTmp_1__1__1_, 
        div_2_u_div_SumTmp_1__1__0_}), .CO(div_2_u_div_CryOut_1__1_) );
  BtoD_DW01_add_51 rem_4_u_div_u_add_PartRem_1_2 ( .A({1'b0, 1'b0, bcd_in[7:3]}), .B({1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_76, SYNOPSYS_UNCONNECTED_77, 
        SYNOPSYS_UNCONNECTED_78, rem_4_u_div_SumTmp_2__1__3_, 
        rem_4_u_div_SumTmp_2__1__2_, rem_4_u_div_SumTmp_2__1__1_, 
        rem_4_u_div_SumTmp_2__1__0_}), .CO(rem_4_u_div_CryOut_2__1_) );
  BtoD_DW01_add_52 div_2_u_div_u_add_PartRem_0_4 ( .A({
        div_2_u_div_PartRem_1__6_, div_2_u_div_PartRem_1__5_, 
        div_2_u_div_PartRem_1__4_, div_2_u_div_PartRem_1__3_, bcd_in[2:0]}), 
        .B({1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_79, SYNOPSYS_UNCONNECTED_80, 
        SYNOPSYS_UNCONNECTED_81, SYNOPSYS_UNCONNECTED_82, 
        SYNOPSYS_UNCONNECTED_83, SYNOPSYS_UNCONNECTED_84, 
        SYNOPSYS_UNCONNECTED_85}), .CO(rem_3_u_div_PartRem_2__1_) );
  BtoD_DW01_add_53 div_2_u_div_u_add_PartRem_1_2 ( .A({1'b0, 1'b0, bcd_in[7:3]}), .B({1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1}), .CI(1'b1), .SUM({
        SYNOPSYS_UNCONNECTED_86, SYNOPSYS_UNCONNECTED_87, 
        SYNOPSYS_UNCONNECTED_88, div_2_u_div_SumTmp_2__1__3_, 
        div_2_u_div_SumTmp_2__1__2_, div_2_u_div_SumTmp_2__1__1_, 
        div_2_u_div_SumTmp_2__1__0_}), .CO(div_2_u_div_CryOut_2__1_) );
  MX2X4 rem_3_u_div_u_mx_PartRem_0_1_0 ( .A(N1), .B(N1), .S0(n83), .Y(
        rem_3_u_div_PartRem_1__1_) );
  MX2X2 rem_3_u_div_u_mx_PartRem_0_0_2 ( .A(rem_3_u_div_PartRem_1__2_), .B(
        rem_3_u_div_SumTmp_0__2_), .S0(rem_3_quotient_0_), .Y(bcd_out[6]) );
  MX2X2 rem_3_u_div_u_mx_PartRem_0_0_0 ( .A(N0), .B(N0), .S0(rem_3_quotient_0_), .Y(bcd_out[4]) );
  MX2X2 rem_3_u_div_u_mx_PartRem_0_0_3 ( .A(rem_3_u_div_PartRem_1__3_), .B(
        rem_3_u_div_SumTmp_0__3_), .S0(rem_3_quotient_0_), .Y(bcd_out[7]) );
  MX2XL rem_3_u_div_u_mx_PartRem_0_0_1 ( .A(rem_3_u_div_PartRem_1__1_), .B(
        rem_3_u_div_SumTmp_0__1_), .S0(rem_3_quotient_0_), .Y(bcd_out[5]) );
  MX2X2 rem_3_u_div_u_mx_PartRem_0_1_1 ( .A(rem_3_u_div_PartRem_2__1_), .B(
        rem_3_u_div_SumTmp_1__1_), .S0(n83), .Y(rem_3_u_div_PartRem_1__2_) );
  MX2X1 rem_3_u_div_u_mx_PartRem_0_1_2 ( .A(n11), .B(rem_3_u_div_SumTmp_1__2_), 
        .S0(n83), .Y(rem_3_u_div_PartRem_1__3_) );
  MX2XL div_1_u_div_u_mx_PartRem_0_1_6 ( .A(bcd_in[7]), .B(
        div_1_u_div_SumTmp_1__6_), .S0(bcd_out[9]), .Y(
        div_1_u_div_PartRem_1__7_) );
  BUFX2 U3 ( .A(div_2_u_div_PartRem_1__4_), .Y(n5) );
  BUFX3 U5 ( .A(rem_4_u_div_PartRem_1__6_), .Y(n7) );
  NAND2X4 U6 ( .A(n69), .B(n68), .Y(rem_4_u_div_PartRem_1__5_) );
  NAND2X2 U7 ( .A(n14), .B(n74), .Y(rem_4_u_div_PartRem_1__6_) );
  AOI22X2 U8 ( .A0(n73), .A1(rem_4_u_div_SumTmp_2__1__3_), .B0(n72), .B1(
        rem_4_u_div_SumTmp_3__1__3_), .Y(n74) );
  INVX6 U9 ( .A(rem_4_u_div_CryOut_3__1_), .Y(n10) );
  NAND2X2 U10 ( .A(n82), .B(rem_3_u_div_SumTmp_0__1_), .Y(n81) );
  NAND2X6 U11 ( .A(n4), .B(n3), .Y(n39) );
  CLKAND2X4 U12 ( .A(n79), .B(div_2_u_div_CryOut_2__1_), .Y(n83) );
  MX2X2 U13 ( .A(div_2_u_div_CryOut_6__0_), .B(div_2_u_div_CryOut_2__0_), .S0(
        n17), .Y(N1) );
  INVX2 U14 ( .A(rem_3_u_div_PartRem_2__1_), .Y(n17) );
  NAND2X2 U15 ( .A(n80), .B(rem_3_u_div_SumTmp_1__1_), .Y(n79) );
  NAND2X5 U16 ( .A(rem_4_u_div_CryOut_6__0_), .B(n13), .Y(n9) );
  NAND2X4 U17 ( .A(n63), .B(rem_4_u_div_CryOut_2__0_), .Y(n8) );
  INVX4 U18 ( .A(rem_4_quotient_2_), .Y(n63) );
  NAND2X2 U19 ( .A(n26), .B(n25), .Y(div_2_u_div_PartRem_1__4_) );
  NAND2X2 U20 ( .A(n28), .B(n27), .Y(div_2_u_div_PartRem_1__5_) );
  NAND2X2 U21 ( .A(n24), .B(n23), .Y(div_2_u_div_PartRem_1__3_) );
  NAND2X2 U22 ( .A(n34), .B(n33), .Y(div_2_u_div_PartRem_1__6_) );
  AOI22XL U23 ( .A0(n32), .A1(div_2_u_div_SumTmp_2__1__3_), .B0(n31), .B1(
        div_2_u_div_SumTmp_3__1__3_), .Y(n33) );
  AOI22XL U24 ( .A0(n30), .A1(bcd_in[5]), .B0(n29), .B1(
        div_2_u_div_SumTmp_1__1__2_), .Y(n28) );
  BUFX2 U25 ( .A(n75), .Y(n14) );
  INVX1 U26 ( .A(div_2_u_div_CryOut_1__1_), .Y(n20) );
  NAND2BXL U27 ( .AN(bcd_in[5]), .B(n78), .Y(div_1_u_div_u_add_PartRem_1_1_n3)
         );
  ADDHXL U28 ( .A(bcd_in[6]), .B(div_1_u_div_u_add_PartRem_1_1_n3), .CO(
        div_1_u_div_u_add_PartRem_1_1_n2), .S(div_1_u_div_SumTmp_1__5_) );
  MXI2XL U29 ( .A(div_2_u_div_CryOut_2__1_), .B(rem_3_u_div_SumTmp_1__3_), 
        .S0(n83), .Y(n1) );
  INVX6 U30 ( .A(n37), .Y(n40) );
  NAND2X4 U31 ( .A(n35), .B(n37), .Y(n3) );
  NAND2X4 U32 ( .A(n36), .B(n40), .Y(n4) );
  AOI22X4 U33 ( .A0(rem_4_u_div_SumTmp_2__1__1_), .A1(n73), .B0(n72), .B1(
        rem_4_u_div_SumTmp_3__1__1_), .Y(n66) );
  NOR2X4 U34 ( .A(n39), .B(n37), .Y(n57) );
  INVX4 U35 ( .A(rem_3_u_div_PartRem_1__1_), .Y(rem_3_u_div_SumTmp_0__1_) );
  INVX6 U36 ( .A(n12), .Y(n13) );
  AND2X6 U37 ( .A(n54), .B(n6), .Y(n70) );
  INVXL U38 ( .A(rem_4_u_div_CryOut_2__1_), .Y(n6) );
  MXI2X6 U39 ( .A(n53), .B(n10), .S0(rem_4_u_div_CryOut_2__1_), .Y(n54) );
  AOI22X4 U40 ( .A0(n73), .A1(rem_4_u_div_SumTmp_2__1__2_), .B0(n72), .B1(
        rem_4_u_div_SumTmp_3__1__2_), .Y(n68) );
  AOI22X4 U41 ( .A0(n13), .A1(rem_4_u_div_CryOut_7__0_), .B0(
        rem_4_u_div_CryOut_3__0_), .B1(n63), .Y(n35) );
  NOR2X4 U42 ( .A(n38), .B(n37), .Y(n58) );
  INVX2 U43 ( .A(rem_3_u_div_PartRem_1__2_), .Y(n82) );
  NAND2X4 U44 ( .A(n67), .B(n66), .Y(rem_4_u_div_PartRem_1__4_) );
  NOR2X3 U45 ( .A(n54), .B(n6), .Y(n73) );
  AOI22X4 U46 ( .A0(n73), .A1(rem_4_u_div_SumTmp_2__1__0_), .B0(n72), .B1(
        rem_4_u_div_SumTmp_3__1__0_), .Y(n55) );
  NAND2X8 U47 ( .A(n9), .B(n8), .Y(n37) );
  AOI22X2 U48 ( .A0(n32), .A1(div_2_u_div_SumTmp_2__1__0_), .B0(n31), .B1(
        div_2_u_div_SumTmp_3__1__0_), .Y(n23) );
  CLKAND2X6 U49 ( .A(n54), .B(rem_4_u_div_CryOut_2__1_), .Y(n72) );
  INVX4 U50 ( .A(rem_4_quotient_2_), .Y(n12) );
  OAI2BB1X4 U51 ( .A0N(rem_3_u_div_PartRem_1__3_), .A1N(n81), .B0(n1), .Y(
        rem_3_quotient_0_) );
  INVX4 U52 ( .A(rem_3_u_div_PartRem_2__1_), .Y(rem_3_u_div_SumTmp_1__1_) );
  BUFX2 U53 ( .A(rem_3_u_div_PartRem_2__2_), .Y(n11) );
  CLKINVX3 U54 ( .A(n39), .Y(n38) );
  NAND2X6 U55 ( .A(n56), .B(n55), .Y(rem_4_u_div_PartRem_1__3_) );
  INVX4 U56 ( .A(div_2_u_div_CryOut_2__1_), .Y(n22) );
  AOI22X2 U57 ( .A0(n30), .A1(bcd_in[3]), .B0(n29), .B1(
        div_2_u_div_SumTmp_1__1__0_), .Y(n24) );
  AOI22X2 U58 ( .A0(n13), .A1(rem_4_u_div_CryOut_5__0_), .B0(
        rem_4_u_div_CryOut_1__0_), .B1(n63), .Y(n36) );
  NOR2X2 U59 ( .A(rem_4_u_div_CryOut_2__1_), .B(n54), .Y(n71) );
  AOI22X1 U60 ( .A0(n30), .A1(bcd_in[6]), .B0(n29), .B1(
        div_2_u_div_SumTmp_1__1__3_), .Y(n34) );
  NOR2X2 U61 ( .A(n22), .B(rem_3_u_div_PartRem_2__2_), .Y(n32) );
  INVX4 U62 ( .A(div_2_u_div_CryOut_3__1_), .Y(n21) );
  AOI22X2 U63 ( .A0(n71), .A1(bcd_in[3]), .B0(n70), .B1(
        rem_4_u_div_SumTmp_1__1__0_), .Y(n56) );
  AOI22X2 U64 ( .A0(n71), .A1(bcd_in[6]), .B0(n70), .B1(
        rem_4_u_div_SumTmp_1__1__3_), .Y(n75) );
  AOI22X2 U65 ( .A0(n71), .A1(bcd_in[5]), .B0(n70), .B1(
        rem_4_u_div_SumTmp_1__1__2_), .Y(n69) );
  AOI22X2 U66 ( .A0(n71), .A1(bcd_in[4]), .B0(n70), .B1(
        rem_4_u_div_SumTmp_1__1__1_), .Y(n67) );
  AOI22X1 U67 ( .A0(n60), .A1(rem_4_u_div_SumTmp_6__0__2_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_7__0__2_), .Y(n49) );
  AOI22X1 U68 ( .A0(n60), .A1(rem_4_u_div_SumTmp_6__0__3_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_7__0__3_), .Y(n61) );
  AOI22X1 U69 ( .A0(n60), .A1(rem_4_u_div_SumTmp_6__0__1_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_7__0__1_), .Y(n45) );
  AOI22X1 U70 ( .A0(n60), .A1(rem_4_u_div_SumTmp_6__0__0_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_7__0__0_), .Y(n41) );
  NOR2X2 U71 ( .A(div_2_u_div_CryOut_2__1_), .B(rem_3_u_div_PartRem_2__2_), 
        .Y(n30) );
  AOI22X4 U72 ( .A0(n22), .A1(n20), .B0(n21), .B1(div_2_u_div_CryOut_2__1_), 
        .Y(rem_3_u_div_PartRem_2__2_) );
  NOR2X2 U73 ( .A(n38), .B(n40), .Y(n60) );
  NOR2X2 U74 ( .A(n40), .B(n39), .Y(n59) );
  CLKINVX4 U75 ( .A(rem_4_u_div_CryOut_1__1_), .Y(n53) );
  AOI22XL U78 ( .A0(rem_3_u_div_PartRem_2__1_), .A1(div_2_u_div_CryOut_7__0_), 
        .B0(div_2_u_div_CryOut_3__0_), .B1(n17), .Y(n19) );
  AOI221XL U79 ( .A0(rem_3_u_div_PartRem_2__1_), .A1(div_2_u_div_CryOut_5__0_), 
        .B0(div_2_u_div_CryOut_1__0_), .B1(n17), .C0(N1), .Y(n18) );
  AOI21X1 U80 ( .A0(n19), .A1(N1), .B0(n18), .Y(N0) );
  NOR2X2 U81 ( .A(n20), .B(div_2_u_div_CryOut_2__1_), .Y(n29) );
  NOR2X1 U82 ( .A(n22), .B(n21), .Y(n31) );
  AOI22XL U83 ( .A0(n30), .A1(bcd_in[4]), .B0(n29), .B1(
        div_2_u_div_SumTmp_1__1__1_), .Y(n26) );
  AOI22XL U84 ( .A0(n32), .A1(div_2_u_div_SumTmp_2__1__1_), .B0(n31), .B1(
        div_2_u_div_SumTmp_3__1__1_), .Y(n25) );
  AOI22XL U85 ( .A0(n32), .A1(div_2_u_div_SumTmp_2__1__2_), .B0(n31), .B1(
        div_2_u_div_SumTmp_3__1__2_), .Y(n27) );
  AOI22XL U86 ( .A0(n58), .A1(bcd_in[0]), .B0(n57), .B1(
        rem_4_u_div_SumTmp_1__0__0_), .Y(n44) );
  AOI22XL U87 ( .A0(n60), .A1(rem_4_u_div_SumTmp_2__0__0_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_3__0__0_), .Y(n43) );
  AOI22XL U88 ( .A0(n58), .A1(rem_4_u_div_SumTmp_4__0__0_), .B0(n57), .B1(
        rem_4_u_div_SumTmp_5__0__0_), .Y(n42) );
  AOI33X1 U89 ( .A0(n44), .A1(n43), .A2(n63), .B0(n13), .B1(n42), .B2(n41), 
        .Y(bcd_out[0]) );
  AOI22XL U90 ( .A0(n58), .A1(bcd_in[1]), .B0(n57), .B1(
        rem_4_u_div_SumTmp_1__0__1_), .Y(n48) );
  AOI22XL U91 ( .A0(n60), .A1(rem_4_u_div_SumTmp_2__0__1_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_3__0__1_), .Y(n47) );
  AOI22XL U92 ( .A0(n58), .A1(rem_4_u_div_SumTmp_4__0__1_), .B0(n57), .B1(
        rem_4_u_div_SumTmp_5__0__1_), .Y(n46) );
  AOI33X1 U93 ( .A0(n48), .A1(n47), .A2(n63), .B0(n13), .B1(n46), .B2(n45), 
        .Y(bcd_out[1]) );
  AOI22XL U94 ( .A0(n58), .A1(bcd_in[2]), .B0(n57), .B1(
        rem_4_u_div_SumTmp_1__0__2_), .Y(n52) );
  AOI22XL U95 ( .A0(n60), .A1(rem_4_u_div_SumTmp_2__0__2_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_3__0__2_), .Y(n51) );
  AOI22XL U96 ( .A0(n58), .A1(rem_4_u_div_SumTmp_4__0__2_), .B0(n57), .B1(
        rem_4_u_div_SumTmp_5__0__2_), .Y(n50) );
  AOI33X1 U97 ( .A0(n52), .A1(n51), .A2(n63), .B0(n13), .B1(n50), .B2(n49), 
        .Y(bcd_out[2]) );
  AOI22XL U98 ( .A0(n58), .A1(rem_4_u_div_PartRem_1__3_), .B0(n57), .B1(
        rem_4_u_div_SumTmp_1__0__3_), .Y(n65) );
  AOI22XL U99 ( .A0(n60), .A1(rem_4_u_div_SumTmp_2__0__3_), .B0(n59), .B1(
        rem_4_u_div_SumTmp_3__0__3_), .Y(n64) );
  AOI22XL U100 ( .A0(n58), .A1(rem_4_u_div_SumTmp_4__0__3_), .B0(n57), .B1(
        rem_4_u_div_SumTmp_5__0__3_), .Y(n62) );
  AOI33X1 U101 ( .A0(n65), .A1(n64), .A2(n63), .B0(n13), .B1(n62), .B2(n61), 
        .Y(bcd_out[3]) );
  CLKINVX1 U102 ( .A(n76), .Y(bcd_out[8]) );
  AOI31X1 U103 ( .A0(div_1_u_div_PartRem_1__6_), .A1(div_1_u_div_PartRem_1__5_), .A2(n77), .B0(div_1_u_div_PartRem_1__7_), .Y(n76) );
  OR3X1 U104 ( .A(div_1_u_div_PartRem_1__2_), .B(div_1_u_div_PartRem_1__4_), 
        .C(div_1_u_div_PartRem_1__3_), .Y(n77) );
  XOR2X1 U105 ( .A(bcd_in[5]), .B(n78), .Y(div_1_u_div_SumTmp_1__4_) );
  NOR2X1 U106 ( .A(bcd_in[4]), .B(bcd_in[3]), .Y(n78) );
  AOI2BB2X1 U107 ( .B0(bcd_in[4]), .B1(div_1_u_div_SumTmp_1__2_), .A0N(
        div_1_u_div_SumTmp_1__2_), .A1N(bcd_in[4]), .Y(
        div_1_u_div_SumTmp_1__3_) );
  CLKINVX1 U108 ( .A(bcd_in[3]), .Y(div_1_u_div_SumTmp_1__2_) );
  XOR2X1 U109 ( .A(div_2_u_div_CryOut_2__1_), .B(n79), .Y(
        rem_3_u_div_SumTmp_1__3_) );
  AOI22XL U110 ( .A0(rem_3_u_div_PartRem_2__1_), .A1(n80), .B0(n11), .B1(
        rem_3_u_div_SumTmp_1__1_), .Y(rem_3_u_div_SumTmp_1__2_) );
  CLKINVX2 U111 ( .A(n11), .Y(n80) );
  XOR2X1 U112 ( .A(rem_3_u_div_PartRem_1__3_), .B(n81), .Y(
        rem_3_u_div_SumTmp_0__3_) );
  AOI22XL U113 ( .A0(rem_3_u_div_PartRem_1__1_), .A1(n82), .B0(
        rem_3_u_div_PartRem_1__2_), .B1(rem_3_u_div_SumTmp_0__1_), .Y(
        rem_3_u_div_SumTmp_0__2_) );
endmodule


module top ( clk, rst, bcd_in, bcd_out_reg );
  input [7:0] bcd_in;
  output [11:0] bcd_out_reg;
  input clk, rst;
  wire   n7, N2, n1, n2, n6, SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2;
  wire   [9:0] bcd_out;
  assign bcd_out_reg[11] = 1'b0;
  assign bcd_out_reg[10] = 1'b0;

  INVXL I_0 ( .A(rst), .Y(N2) );
  DFFTRX4 bcd_out_reg_reg_8_ ( .D(N2), .RN(bcd_out[8]), .CK(clk), .Q(
        bcd_out_reg[8]) );
  DFFTRX4 bcd_out_reg_reg_7_ ( .D(N2), .RN(bcd_out[7]), .CK(clk), .Q(
        bcd_out_reg[7]) );
  DFFTRX4 bcd_out_reg_reg_6_ ( .D(N2), .RN(bcd_out[6]), .CK(clk), .Q(
        bcd_out_reg[6]) );
  DFFTRX4 bcd_out_reg_reg_4_ ( .D(N2), .RN(bcd_out[4]), .CK(clk), .Q(
        bcd_out_reg[4]) );
  BtoD inst_BtoD ( .bcd_in(bcd_in), .bcd_out({SYNOPSYS_UNCONNECTED_1, 
        SYNOPSYS_UNCONNECTED_2, bcd_out}) );
  DFFTRX4 bcd_out_reg_reg_3_ ( .D(N2), .RN(bcd_out[3]), .CK(clk), .Q(
        bcd_out_reg[3]) );
  DFFTRX4 bcd_out_reg_reg_1_ ( .D(N2), .RN(bcd_out[1]), .CK(clk), .Q(
        bcd_out_reg[1]) );
  DFFTRX4 bcd_out_reg_reg_0_ ( .D(N2), .RN(bcd_out[0]), .CK(clk), .Q(
        bcd_out_reg[0]) );
  DFFTRX2 bcd_out_reg_reg_2_ ( .D(N2), .RN(bcd_out[2]), .CK(clk), .Q(n7) );
  AND2X1 bcd_out_reg_reg_9__U2 ( .A(N2), .B(bcd_out[9]), .Y(n6) );
  DFFRQX4 bcd_out_reg_reg_9_ ( .D(n6), .CK(clk), .RN(1'b1), .Q(bcd_out_reg[9])
         );
  DFFTRXL bcd_out_reg_reg_5_ ( .D(N2), .RN(bcd_out[5]), .CK(clk), .QN(n1) );
  INVXL U3 ( .A(n7), .Y(n2) );
  CLKINVX4 U4 ( .A(n2), .Y(bcd_out_reg[2]) );
  CLKINVX4 U5 ( .A(n1), .Y(bcd_out_reg[5]) );
endmodule

